ICs may include memory cells, such as dynamic random access memory (DRAM) cell for storing information. A plurality of memory cells is interconnected by wordlines and bitlines to form a memory block or array. The bitlines are coupled to sense amplifiers to facilitate memory accesses. Typically, a pair of bitlines (first and second bitlines) is coupled to a sense amplifier. The sense amplifier senses a differential signal on the bitline pair during a read operation and amplifies it. The differential signal is indicative of the data stored in the selected memory cell. After the differential signal is sufficiently amplified, it is gated to a data line which forwards the signal onto the output data path.
A memory array can be divided into a plurality of banks. Each bank is usually provided with at least one data line which is commonly coupled to the sense amplifiers of the bank. When a particular sense amplifier is selected to output its amplified signal onto the data line according to a gating signal supplied from the column decoder, the output of the sense amplifier is connected to the data line.
The data line has a considerable capacitance, which can adversely affect the integrity of the amplified signal. In some cases, the amplified signal can be destroyed by being forced to a level of the read signal from the previous operation cycle. For example, if the amplified signal from the sense amplifier of the current cycle is of the opposite logic level from that of the previous cycle, the signal of the previous cycle may prevent the signal from the current cycle to be driven onto the data lines within the given time. This is generally known as the kickback effect, which leads to read errors.
In order to avoid kickback errors during read operations, the amplified signal from the amplifier needs to be sufficiently strong to drive the data line to the desired level. This requires the sufficient amplification time to ensure that the amplified differential signal can invert the signal on the data line from the previous cycle, thus decreasing performance as well as increasing power consumption.
From the above discussion, it is desirable to increase read performance without incurring higher power consumption in, for example, memory ICs.
The invention relates to Improving performance for ICs with memory cells. In one embodiment, improved performance is achieved by providing faster access to the memory array. In one embodiment, a precharge circuit is provided for the data line coupled to the memory array. The precharge circuit, when activated, pulls the potential of the data line to a precharge potential. Preferably, the precharge level is in the middle between the positive and the negative (e.g., ground) supply potentials. The precharging level is preferably the same level as the precharging level that is provided to the bitlines before the sensing operation.
In one embodiment, the precharge circuit comprises a switch for selectively coupling the data line to a supply voltage equal to the precharge voltage level. The precharge circuit, in one embodiment, is controlled by the precharge control signal used to control the precharging of the bitlines.
In one embodiment, after having completed a first read or write operation on a data line, the potential on the data line is forced to the precharge potential. During the next read operation, the data line is brought to a high level or a low level depending on the signal from the sense amplifier. The signal swing is only half of the full signal amplitude between a low level signal and a high level signal. As such, the charging of the data line from the precharge potential to the high level or the low level data signal which may be the positive or the negative power supply potential is achieved faster than a full level swing from a low level signal to a high level signal, or vice-versa.